The present invention relates to a switching voltage regulator circuit, and more particularly to a control circuit for maintaining high operational efficiency across a broad range of input and output voltages in a switching voltage regulator circuit.
In integrated circuits (IC), there is often a need to generate a lower DC voltage from a higher DC supply voltage that is relatively unstable and noisy. A voltage regulator is often required to operate under a relatively wide range of input voltages and to have a programmable output voltage. One known circuit for achieving this is commonly referred to as a pulse width modulated (PWM) voltage regulator, a simplified block diagram of which is shown in FIG. 1. PWM regulator 10 is shown as including a PWM signal generator 20, a driver 25, an inductor 30, a load resistor 40 and a feedback controller 45. Supply voltage Vin is pulse-width modulated by PWM regulator 10 and is subsequently supplied as output voltage signal VOUT. Resistive load 40 is typically externally supplied. Feedback controller 45 is adapted to maintain VOUT nearly equal to reference voltage VREF and further to maintain stability in the loop.
FIG. 2 is a simplified schematic diagram of driver 25 in communication with inductor 30, capacitor 35 and load resistor 40, as known in the prior art. Driver 25 is shown as including switches Sw1 and Sw2 that respectively enable inductor 30 to be charged and discharged. FIG. 3 shows the inductor current as a function of the on/off periods of switches Sw1 and Sw2. During each switching period Tsp, switch Sw1 is on for a first fixed period T1, switch Sw2 is on for a second fixed period T2, and both switches are off for a third fixed period T3. During period T1, inductor 30 is charged in accordance with the following expression:
                    i        L            ⁡              (        t        )              =                  I                  L          ⁢                                          ⁢          0                    +                        1          L                ⁢                              ∫            0            t                    ⁢                      v            IN                              -                        v          out                ⁢                  ⅆ          t                      ,where L is the inductance of inductor 30. Likewise, during the period T2 inductor 30 is discharged in accordance with the following expression:
            i      L        ⁡          (      t      )        =            I              L        ⁢                                  ⁢        0              -                  1        L            ⁢                        ∫          0          t                ⁢                              v            OUT                    ⁢                                    ⅆ              t                        .                              
Assume, for example, that regulator 10 is designed to receive a maximum input voltage of 5 volts and supply a minimum output voltage of 0.6 volts. Assume regulator 10 is also adapted to operate in the pulse-frequency modulation (PFM) mode. Accordingly, period T1 would be fixed to approximately 10% of the switching period. If a user decides to use regulator 10 under a different input/output operating conditions, such as to convert an input voltage of 3.2 volts to an output voltage of 1.6 volts, because the period T1 is fixed, a significant amount of time during each switching period that could otherwise be used to charge and discharge inductor 30 would be wasted. Regulator 10 is thus inefficient.
FIGS. 4A and 4B show an exemplary 16 cycles of a switching period TSP of regulator 10. In FIG. 4A, the charging period T1, i.e., the period during which signal A is asserted to charge the inductor, is relatively short. Therefore, period T3, during which both switches are non-conductive, cannot be used to charge the inductor. The inductor current IL remains zero during this period. In FIG. 4B, the charging period is relatively long thus inhibiting the inductor to be fully discharged, in turn, causing the current during the next period to be higher and output voltage ripple to increase.